By Mikhail Kovalev,Silvia M. Müller,Wolfgang J. Paul

ISBN-10: 3319139053

ISBN-13: 9783319139050

This monograph relies at the 3rd author's lectures on computing device structure, given in the summertime semester 2013 at Saarland collage, Germany. It incorporates a gate point building of a multi-core desktop with pipelined MIPS processor cores and a sequentially constant shared memory.

The booklet comprises the 1st correctness proofs for either the gate point implementation of a multi-core processor and likewise of a cache established sequentially constant shared reminiscence. This opens how one can the formal verification of synthesizable for multi-core processors within the future.

Constructions are in a gate point version and therefore deterministic. by contrast the reference types opposed to which correctness is proven are nondeterministic. the advance of the extra equipment for those proofs and the correctness facts of the shared reminiscence on the gate point are the most technical contributions of this work.

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A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness Proof (Lecture Notes in Computer Science) by Mikhail Kovalev,Silvia M. Müller,Wolfgang J. Paul

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